module top wire [1:0]A; wire [1:0]B; wire [1:0]S; wire Cout; system_clock #800 clock (B[1]); system_clock #400 clock (B[0]); system_clock #200 clock (A[1]); system_clock #100 clock (A[0]); system_clock #50 clock (Cin); adder2 ad(A,B,Cin,S,Cout); endmodule module adder(A,B,Cin0,S,Cout0); input A,B,Cin0; output Cout0,S; wire Ci,Co,Si; assign {Ci,Si}=A+B; assign {Co,S}=Cin0+Si; or (Cout0,Ci,Co); endmodule module adder2(A,B,Cin,S,Cout); input [1:0]A,B; input Cin; output Cout; output [1:0]S; wire e; adder h1(A[0],B[0],Cin,S[0],e); adder h2(A[1],B[1],e,S[1],Cout); endmodule module system_clock(clk); parameter PERIOD=100; output clk; reg clk; initial clk=0; always begin #(PERIOD/2)clk=~clk; end endmodule